module ForwordAlu(
    input [4:0]  rs,
    input [4:0]  rt,
    input [4:0]  ex_mem_des_reg,
    input        ex_mem_RegWrite,
    input [4:0]  mem_wb_des_reg,
    input        mem_wb_RegWrite,
    output reg [1:0] rs_hazard,
    output reg [1:0] rt_hazard   
); 

   parameter NO_HAZARD = 2'b00,HAZARD_EX_MEM = 2'b01,HAZARD_MEM_WB=2'b10;
   always @(*) begin
        if(rs==ex_mem_des_reg&&ex_mem_RegWrite&&ex_mem_des_reg!=0)
                rs_hazard = HAZARD_EX_MEM;
        else if(rs==mem_wb_des_reg&&mem_wb_RegWrite&&mem_wb_des_reg!=0)
                rs_hazard = HAZARD_MEM_WB;
        else 
                rs_hazard = NO_HAZARD;
        
        if(rt==ex_mem_des_reg&&ex_mem_RegWrite&&ex_mem_des_reg!=0)
                rt_hazard = HAZARD_EX_MEM;
        else if(rt==mem_wb_des_reg&&mem_wb_RegWrite&&mem_wb_des_reg!=0)
                rt_hazard = HAZARD_MEM_WB;
        else 
                rt_hazard = NO_HAZARD;
   end

endmodule


module ForwordBranch(

    input [1:0] Branch,
    input [4:0]  rs,
    input [4:0]  rt,
    input [4:0]  ex_mem_des_reg,
    input        ex_mem_RegWrite,
    input [4:0]  mem_wb_des_reg,
    input        mem_wb_RegWrite,
    output reg [1:0] rs_hazard,
    output reg [1:0] rt_hazard   
); 

   parameter NO_HAZARD = 2'b00,HAZARD_EX_MEM = 2'b01,HAZARD_MEM_WB=2'b10;
   always @(*) begin
        if(Branch)
        begin
                if(rs==ex_mem_des_reg&&ex_mem_RegWrite&&ex_mem_des_reg!=0)
                        rs_hazard = HAZARD_EX_MEM;
                else if(rs==mem_wb_des_reg&&mem_wb_RegWrite&&mem_wb_des_reg!=0)
                        rs_hazard = HAZARD_MEM_WB;
                else 
                        rs_hazard = NO_HAZARD;
                
                if(rt==ex_mem_des_reg&&ex_mem_RegWrite&&ex_mem_des_reg!=0)
                        rt_hazard = HAZARD_EX_MEM;
                else if(rt==mem_wb_des_reg&&mem_wb_RegWrite&&mem_wb_des_reg!=0)
                        rt_hazard = HAZARD_MEM_WB;
                else 
                        rt_hazard = NO_HAZARD;     
        end
        else
        begin
                rs_hazard = NO_HAZARD;
                rt_hazard = NO_HAZARD;
        end
   
   end

endmodule